The present invention relates to a frequency divider having an adjustable division factor, including an input and a divider cell with an input for accepting a first signal at a first frequency and an output for outputting a second signal at a second frequency, and a power control means associated with the frequency divider to adjust a bias current of the divider cell.
Such a frequency divider is known from Application Note 4 xe2x80x98Using the PE3291/92 in CDMA Applicationsxe2x80x99 from Peregrine Semiconductor Corporation. The PE3291 is a fractional-N PLL integrated frequency synthesizer and contains two dividers: a 16/17 modulus prescaler (PLL1) and a 32/33 modulus prescaler (PLL2) with variable division factors. The PE 3291 provides two inputs VDD1 and VDD2 which allow external control of the bias level of the prescaler PLL1 and the prescaler PLL2. When a prescaler is used at a reduced speed, the bias level can be reduced. The prescaler is slower at lower bias levels, but a bias level can be chosen such that the speed is adequate for the operation at a reduced input frequency. In this way the power consumption can be reduced in relation to the reduced input frequency.
A disadvantage of the known frequency divider is that the power consumption cannot be reduced substantially.
It is an object of the present invention to provide a circuit where the power consumption of the frequency divider can be reduced.
To achieve this, the frequency divider is characterized in that the frequency divider includes a multiplexing means with a first input for receiving the second signal with the second frequency and a second input for receiving a third signal with a third frequency and an output for outputting either the second signal or the third signal, where the first input of the multiplexing means is connected to the output of the divider cell and in that the power control means is operative to reduce the bias current of the divider cell to zero when the first input of the multiplexing means is deselected.
Frequency dividers having programmable division factors are often employed in a system with different input frequencies. The programmable division factor enables the system to divide the input frequency to yield a frequency that is within a prescribed operating range.
An example of this is the use of a divider with a programmable division factor in a Phase Locked Loop (PLL). The input frequency varies, and the frequency divider is used to divide the input frequency to a frequency range that is required for the phase detector to work properly.
If the input frequency of the frequency divider is reduced, the division factor must be reduced.
When the division factor is reduced, some divider cells of the frequency divider are no longer needed to divide the signal. These cells are then deselected by a multiplexer and the multiplexer obtains its input signal from another point in the frequency divider. Since the output of the divider cell is no longer used, the bias current of the divider cell can be reduced to zero, in effect switching the divider cell off and reducing the power consumption of this divider cell to zero. The power consumption of the frequency divider is thus dependent on the division factor of the frequency divider.
In the GSM mobile radio system two frequencies are employed, e.g. 900 MHz and 1800 MHz.
When a mobile phone is operating in the 900 MHz band, the frequency divider in the PLL generating the carrier frequency must divide the VCO frequency by a factor of 2 less than when the mobile phone is operating in the 1800 MHz band. If the frequency divider contains a divider cell of two that divides the signal coming from the input, this divider is not needed when working in the 900 MHz band. The signal does not need to pass through this divider cell and, consequently, the divider cell can be switched off.
An embodiment of the present invention is characterized in that the second input of the multiplexing means is connected to the input of the divider cell.
By selecting the input of the divider cell instead of the output of the divider cell, the input signal will appear undivided on the output of the multiplexer. By switching the multiplexer, the division factor of the combination of the multiplexer and the divider cell can be switched between 1 and the division factor of the divider cell. The multiplexer provides the frequency divider with the option to bypass the divider cell. Since the divider cell is not used, it is possible to reduce the bias of the divider cell to zero and thus reduce the power consumption of the frequency divider.
A further embodiment of the present invention is characterized in that the frequency divider includes a further multiplexing means, which is referred to as the second multiplexing means, with a first input and a second input and an output, where the first input of the second multiplexing means is connected to the output of the second divider cell and where the second input of the second multiplexing means is connected to the second input of the multiplexing means and in that the second power control means is operative to reduce the bias current of the second divider cell to zero when the first input of the second multiplexing means is deselected.
A further embodiment of the present invention is characterized in that at least one power control means associated to the divider cell is operative to adjust the bias current of the associated divider cell proportionally to an input frequency of the divider cell when the first input of the multiplexing means connected to the output of that divider cell is selected.
When a divider cell is not operating at the maximum operating frequency, the bias current of this divider cell can be reduced, thereby reducing the effective speed of the divider cell. The power dissipation can be optimized by adjusting the bias current to a level just above the level where the operation of the divider would be adversely affected. In this way a gradual reduction of power dissipation can be achieved between the power reduction steps obtained by bypassing and switching off entire divider cells when the operating frequency is reduced.
A further embodiment of the present invention is characterized in that a microprocessor is operative to control the VCO and at least one of the power control means of the frequency divider.
The microprocessor controls the VCO and, therefore, knows what the operating frequency of the VCO is and also knows what the required division factor of the frequency divider is. Based on the required division factor, the microprocessor decides which divider cells are not needed, switches those divider cells off, and switches the associated multiplexers so that these divider cells are bypassed. Based on the operating frequency, the microprocessor can also reduce the bias current for the remaining, operative, divider cells to further optimize the power consumption of the frequency divider.
A further embodiment of the present invention is characterized in that a third power control means is operative to adjust the amplifier bias current of the input amplifier dependent of an input frequency of the input amplifier.